This invention relates to the sensing of NVM (Non-Volatile Memory) semiconductor cells and, in particular, sensing the NVM memory cells by differential pair current sensing techniques.
There are many types of NVM semiconductor cells, such as ROM (Read-Only Memory), EPROM (Erasable ROM), EEPROM (Electrically Erasable ROM), flash memory and OTP (One-Time Programmable) cells. In a NVM memory, the conventional sensing technique is a single-ended with the voltage developed on a selected bit line compared to an analog reference voltage. That is, to read the data in a selected NVM memory cell, only a single line, the bit line, from the NVM memory cell is used to sense the data in the NVM memory cell in a reading operation.
On the other hand, in some of the assignee's applications the bit line and its complementary bit line of the selected NVM memory cells are differentially sensed. That is, in the programming of a selected memory cell there are two possibilities: that the cell connected to the bit line is to be programmed or a related cell connected to the complementary bit line is to be programmed. Hence to read the contents of a memory cell at a particular address, there are two available memory cells, each with complementary programmed states. This allows for current differential sensing, such as found in SRAM (Static Random Access Memory) integrated circuits, in which the sense amplifier of cross-coupled inverter circuits permit the complementary states of the selected memory cell and its complement to pull the sense amplifier into one state or its complementary state quickly.
However, for reading the NVM memory cells in their pre-programmed states, the current differential technique for SRAM integrated circuits cannot be used. By definition there is no pair of programmed and unprogrammed memory cells; except for faulty cells, all preprogrammed memory cells are supposedly unprogrammed. Hence another circuit must be used for reading the memory cell prior to programming. Presently a current differential sense technique is used with 2 cycles of sensing. One cycle is for the bit line and the other cycle is for complementary bit line by alternating connections of the bit line and the complementary bit line into an operational amplifier (OP comparator). This technique allows for the integrity of the memory cells at the pre-programmed stage to be checked.
Hence it would desirable to take advantage of the described memory structure to achieve a fast current sensing scheme using differential currents between the bitline and the complementary bitline. The invention uses the SRAM sensing architecture for normal sensing and expands it into current sensing for reading and detecting faults in preprogrammed NVM memory cells.